Implementation of Sram Array by Using Multibit Flip-flop
نویسنده
چکیده
Memory elements play a vital role on Digital World. In memory devices the most important factor is power consumption. Because the power consumption of the memory device increases means, the device reliability and life time is reduced. The basic memory elements of designer considerations are Latch and Flip-flop. In this paper we design SRAM using arrays of flip-flops and we analyze the design of Single-bit Flipflop (SBFF i.e., 1bit) and made performance comparison over the Multi-bit Flip-flop (MBFF i.e., 2bit, 4bit, 8bit, 16bit, and 32bit). While designing the memory by using SBFF means it consumes more power. To get maximum reduction in power an algorithm has been proposed in which Single-bit flip flops are replaced with maximum possible Multi-bit Flip-flop without affecting the performance of the original circuit. This paper analyzes the timing performance of both SBFF and MBFF in Xilinx Virtex-5 family (XC5VLX50). These results in favour of Multi-Bit Flip-flop as reduction of power and area.
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